This application claims priority on Korean application number 2000-37397, filed Jun. 30, 2000 in the name of Samsung Electronics Co., Ltd. and is herein incorporated by reference for all purposes.
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interdielectric layer having openings by using a difference in an etch-rate and for forming a conductive contact for filling the openings.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the misalignment margins in a photolithographic process becomes narrower. As a result, it is not easy to achieve the necessary misalignment margin when manufacturing the semiconductor devices. Thus, an electrical short-circuit can occur between a gate line and a contact pad adjacent to the gate line, or between a bit line and a buried contact (BC) adjacent to the bit line, or between the gate line and the BC or a direct contact (DC).
In order to overcome this problem, a self aligned contact (SAC) etching process has been implemented. However, the SAC etching process has limitations in views of non-opening and a selectivity.
In detail, since the bonding energy of silicon dioxide (SiO2), which used as an interdielectric layer, is large, the interdielectric layer does not have a very high etching selectivity with respect to silicon nitride (Si3N4), which is used to form a spacer. As a result, it is necessary to increase the thickness of the spacer, and due to the increased thickness of the spacer, the interval between the gate lines becomes narrower and the aspect ratio increases.
Due to the increase in the aspect ratio when forming the contact hole, it is more difficult to obtain the bottom critical dimension of the contact hole. As a result, a defect occurs in which the hole does not open properly. Also, the increase in the aspect ratio of the contact hole causes filling failures such as voids or seams in the interdielectric layer when filling the contact hole.
To solve the above problems, it is a feature of the present invention to provide a method for forming a conductive contact. The method is capable of preventing an electrical short-circuit and preventing a contact hole from not opening, while realizing a high etch selectivity with respect to a spacer when forming the contact hole, thereby reducing the required thickness of the spacer and allowing the spacerto be formed of a material having a low dielectric constant.
Accordingly, to achieve the above feature, according to one aspect of the present invention, a dummy dielectric layer comprised of insulating materials having a relatively high etch-rate and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer are formed on a semiconductor substrate. The dummy dielectric layer is selectively removed by using a high etching selectivity between the dummy dielectric layer and the interdielectric layer pattern, and thereby forming a contact opening exposing a portion in which a contact will be formed.
Here, the dummy dielectric layer is formed of an organic material, and the interdielectric layer pattern is formed of a silicon dioxide (SiO2) layer which is in one preferred embodiment, selectively deposited from a liquid phase precursor.
Meanwhile, in order to form the contact opening, the dummy dielectric layer is selectively etched, to form a dummy opening which exposes a portion in which the contact body is not formed: The interdielectric layer is then formed to fill the dummy opening. The dummy dielectric material remaining in the contact area is then selectively etched to form the contact opening. The contact opening is filled with conductive materials and divided into the contact body by using surface etching or polishing.
According to the present invention, by introducing the dummy dielectric layer pattern formed of the organic material, the defects that occur when forming the contact opening can be minimized.